Modelling electrical properties of thin high-k gate stacks (HfSiO, 70% Hf)

These formulas have been used: and C MAX has been calculated in task 2, which is 2.92Nf. assuming that it is a uniformly doped semiconductor, then and, so that,   It is not a simple function and cannot be calculate directly, in this case, we use MATLAB to calculate the N A , and N A =4.2*10 21 m -3

 The equivalent oxide thickness is stated as a distance, which imply the thickness of silicon oxide that is required to get the similar effect as using high-k materials. The term is commonly used to describe the field effect transistors and is often given in nanometers. These formulas have been used: so that, and we can figure out that ε hk=10.6506 while ， we can get that EOT=2.8084nm.

  The oxide relative permittivity can be calculated using the mathematical characteristics of capacitors under the accumulation region (which is the highest region of the C-V plot). Under the accumulation condition, the MOS capacitor can be seen as the series connection of the C ox and C acc .            As C acc is exponentially dependent on and therefore very large.  (C acc =dC acc /d Φ S )  So, in above equation, the term of accumulation capacitance can be ignored and the total capacitance can be seen equal to oxide capacitance. Then we can obtain the oxide capacitance by reading the max value from the C-V plot, from given data, the value is 2.92E+03pF. Then we can calculate the oxide relative permittivity through function below: With given data, we have: By substituting equations 2.2 to 2.5 into equation 2.1, we obtained  ε ox =6.8.

  The data was allocated in txt format and we put them into excel and obtained this C-V plot. Figure 1: C-V plot C-V plot (HfSiO, 70% Hf). According to the plot drawn from given data, the substrate involved in this project is p type. This conclusion is made from the characteristic of surface field effect. There are three conditions of the energy band diagram, accumulation, depletion and inversion. Under the accumulation condition of p type Si MOS system, when negative voltage is applied on the gate, positive holes in the semiconductor will be attracted to the region close to the oxide and accumulate there. When voltage applied on the gate increases to positive, the positive holes accumulated before will be repelled and leave behind some negative acceptances. Then this condition is called depletion condition. Finally, when the gate voltage is high enough, the fermi level of semiconductor in the region near to the oxide will be bend higher than the intrinsic level, and thus...

  The object of this project is thin high-k gate stacks (HfSiO, 70%), which is bind up with MOSFET, while silicon-based integrated circuits have developed rapidly in the past years. High-k dielectric materials are one of the most popular research topics in the micro electronic industry. By using some special properties of some high-k dielectric materials, some new devices may be conducted and the limitation of the thin gate-oxide faced in semiconductor industry may be solved. Electronics based on these improve the life quality and make our life more comfortable, like internet and mobile phones. On the basis of Moore’s law, the number of transistors on the integrated circuits doubled every two years, so that the gate stacks become the concern issue. Scientists and engineers made great efforts to incorporate the high-k dielectric into a transistor. According to SIA [1], in order to maintain the development speed of the semiconductor, researchers should develop constraints like new ...