Further Research

 

It is known that "Fermi pinning phenomenon" occurs between high-k gate oxide and polysilicon gate and the compatibility between high-k gate oxide and polysilicon gate is poor [2]. Research shows that using metal gate technology, HK/MG (high-k/metal gate) can improve the performance of the transistor and consume less power. In addition, compared with the gate-first HK/MG technology, the gate-last HK/MG technology will gradually become the main manufacturing process for the HK/MG in terms of high performance or low power consumption. However, the manufacturing technology of gate-last HK/MG is complex and the yield is low, which makes it difficult to achieve large-scale mass production. Moreover, the customer manufacturers need to modify the circuit design according to the needs. Therefore, for the HK/MG technology, the future research direction may be the improvement of the gate-last HK/MG technology, as one of the future research directions of planar transistors. Looking beyond the 22nm node, transistors may change from traditional planar gate to multi gate [3]. Intel announced in 2011 that the three-dimensional 3D Tri-Gate transistor, compared with the planar transistor, not only has better performance, but also is widely used, which may be the focus of transistor research and development in the future.

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Task 2 Determine the Oxide Relative Permittivity (εr or k)

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  The oxide relative permittivity can be calculated using the mathematical characteristics of capacitors under the accumulation region (which is the highest region of the C-V plot). Under the accumulation condition, the MOS capacitor can be seen as the series connection of the C ox and C acc .            As C acc is exponentially dependent on and therefore very large.  (C acc =dC acc /d Φ S )  So, in above equation, the term of accumulation capacitance can be ignored and the total capacitance can be seen equal to oxide capacitance. Then we can obtain the oxide capacitance by reading the max value from the C-V plot, from given data, the value is 2.92E+03pF. Then we can calculate the oxide relative permittivity through function below: With given data, we have: By substituting equations 2.2 to 2.5 into equation 2.1, we obtained  ε ox =6.8.
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Task5. Work Function Difference (Calculate the work function difference assuming a gold (Au) gate.）

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  The work function Ф M is defined as the minimum energy required for an electron with an energy equal to Fermi level to escape from the metal into vacuum. It is shown in figure 2. For metals, the work function Ф M = Ф VA - Ф FM is constant. Thus,  Ф M (Au)=5.1eV. For semiconductors, the work function is: which is shown in figure 2. According to known conditions, the electron affinity of Si is and the Bandgap energy of silicon is The Fermi potential Ф F is equal to and is about 25mV at 300k. Thus, Fermi potential: and the work function of semiconductors: The definition of Mental-Semiconductors work function difference is: Thus, the work function difference: Figure 2: Energy band diagram explaining work function
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Task 6. Flatband voltage (Calculate the flatband voltage）

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  Flatband voltage is defined as the gate voltage when the band of semiconductor is not bent as shown in figure 3. In ideal case, V G =0   In actual case, V G ≠ 0. There are two reasons. The first one is that there is a work function difference between the metal and the semiconductor. The second one is that the net charge density in the oxide layer is actually non-zero, such as Fixed charge of oxide. Figure 3: Band diagram of flat band As V G is gradually reduced, the accumulation capacitance becomes smaller and has the effect of reducing the measured capacitance. When V G is equal to zero volts. The semiconductor capacitance is now defined by the so-called Debye length: thus: Figure 4: The a.c. equivalent circuit at flatband. thus: The area: Then, The corresponding Flatband voltage V FB is close to 0.93 V.
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