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Task 6. Flatband voltage (Calculate the flatband voltage）

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  Flatband voltage is defined as the gate voltage when the band of semiconductor is not bent as shown in figure 3. In ideal case, V G =0   In actual case, V G ≠ 0. There are two reasons. The first one is that there is a work function difference between the metal and the semiconductor. The second one is that the net charge density in the oxide layer is actually non-zero, such as Fixed charge of oxide. Figure 3: Band diagram of flat band As V G is gradually reduced, the accumulation capacitance becomes smaller and has the effect of reducing the measured capacitance. When V G is equal to zero volts. The semiconductor capacitance is now defined by the so-called Debye length: thus: Figure 4: The a.c. equivalent circuit at flatband. thus: The area: Then, The corresponding Flatband voltage V FB is close to 0.93 V.
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Task 1 The Plot of the C-V Curve

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  The data was allocated in txt format and we put them into excel and obtained this C-V plot. Figure 1: C-V plot C-V plot (HfSiO, 70% Hf). According to the plot drawn from given data, the substrate involved in this project is p type. This conclusion is made from the characteristic of surface field effect. There are three conditions of the energy band diagram, accumulation, depletion and inversion. Under the accumulation condition of p type Si MOS system, when negative voltage is applied on the gate, positive holes in the semiconductor will be attracted to the region close to the oxide and accumulate there. When voltage applied on the gate increases to positive, the positive holes accumulated before will be repelled and leave behind some negative acceptances. Then this condition is called depletion condition. Finally, when the gate voltage is high enough, the fermi level of semiconductor in the region near to the oxide will be bend higher than the intrinsic level, and thus...
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References

  [1]: International Technology Roadmap for Semiconductors , [online] Available: http://www.itrs.net/mtrs/publntrs.nsf [2] S. K. Kundu et al,, "A study on high-κ gate stack for MOS-FET," 2015 International Conference and Workshop on Computing and Communication (IEMCON) , pp. 1-5, Oct. 2015. [3] Thomas Y. Hoffmann. (2010, March) Integrating high-k /metal gates: gate-first or gate-last? [Online]. Available: https://sst.semiconductor-digest.com/2010/03/integrating-high-k/
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