Modelling electrical properties of thin high-k gate stacks (HfSiO, 70% Hf)

  [1]: International Technology Roadmap for Semiconductors , [online] Available: http://www.itrs.net/mtrs/publntrs.nsf [2] S. K. Kundu et al,, "A study on high-κ gate stack for MOS-FET," 2015 International Conference and Workshop on Computing and Communication (IEMCON) , pp. 1-5, Oct. 2015. [3] Thomas Y. Hoffmann. (2010, March) Integrating high-k /metal gates: gate-first or gate-last? [Online]. Available: https://sst.semiconductor-digest.com/2010/03/integrating-high-k/

  It is known that "Fermi pinning phenomenon" occurs between high-k gate oxide and polysilicon gate and the compatibility between high-k gate oxide and polysilicon gate is poor [2]. Research shows that using metal gate technology, HK/MG (high-k/metal gate) can improve the performance of the transistor and consume less power. In addition, compared with the gate-first HK/MG technology, the gate-last HK/MG technology will gradually become the main manufacturing process for the HK/MG in terms of high performance or low power consumption. However, the manufacturing technology of gate-last HK/MG is complex and the yield is low, which makes it difficult to achieve large-scale mass production. Moreover, the customer manufacturers need to modify the circuit design according to the needs. Therefore, for the HK/MG technology , the future research direction may be the improvement of the gate-last HK/MG technology, as one of the future research directions of planar transistors. Looking be...

    According to the experiment and tasks we finished, it is a summing-up to whole project.   The relative permittivity of HFSiO4 is 10.6 and the relative permittivity of SiO 2 is 3.9, thus the relative permittivity of the oxide layer increased with the concentration of Hf. EOT is 2.8nm, which thinner than the thickness of the gate stack 4.9nm.   The doping density of the silicon substrate is 4.8*10 21 m -3 , this value will be used in later calculations. The work function difference assuming a gold (Au) gate is equal to 0.08eV, this work function can also be used to calculate the V G at mid-gap condition. The results of problem 6 and problem 7 are the base of calculate oxide charge density and the corresponded charges number.   The charge number of flatband condition is less than the mid-gap condition. This is the influence of deltaV, deltaV equals V G subtracting V midgap , and it will cause the shifting of C-V curve as figure 6. Ideal C-V c...

  This problem should be discussed in two situations. First, the oxide charge density at the flat-band condition. By using this formula: The value of Qox is -1.045* 10 6 C/cm 2 Then, we can use this formula to calculate the count of charges. We know the value of q, this is a common value, 1.602*10 -19 Then the value of N OX is 6.52*10 12 Second, at mid-gap situation, we need different formulas to calculate the value of Q OX , and there are the formulas: After calculate the value of VG , deltaV is 0.422-1.35=-0.928V, and we also knew the value  of area, so Q OX is  -1.14*10 -6 C/cm 2 In the end, the value of N OX at mid-gap condition is 7.116*10 12

 To calculate the mid-gap voltage, we need to obtain the depletion capacitor value at mid-gap.                                           Figure5. The a.c. equivalent circuit at mid-gap Assuming a uniformly doped semiconductor, we can calculate the depletion capacitor value by the formula: Then, the value of C dep   is 3.28E-4 F/m 2 Using the formula: we can calculate the value of 1/C midgap . And we know the relationship between C Dep and C dep . With the values of C Dep and C OX , we can calculate the value of C midgap is 7.587*10 -11 F, and V midgap equals 1.35V.

  Flatband voltage is defined as the gate voltage when the band of semiconductor is not bent as shown in figure 3. In ideal case, V G =0   In actual case, V G ≠ 0. There are two reasons. The first one is that there is a work function difference between the metal and the semiconductor. The second one is that the net charge density in the oxide layer is actually non-zero, such as Fixed charge of oxide. Figure 3: Band diagram of flat band As V G is gradually reduced, the accumulation capacitance becomes smaller and has the effect of reducing the measured capacitance. When V G is equal to zero volts. The semiconductor capacitance is now defined by the so-called Debye length: thus: Figure 4: The a.c. equivalent circuit at flatband. thus: The area: Then, The corresponding Flatband voltage V FB is close to 0.93 V.

  The work function Ф M is defined as the minimum energy required for an electron with an energy equal to Fermi level to escape from the metal into vacuum. It is shown in figure 2. For metals, the work function Ф M = Ф VA - Ф FM is constant. Thus,  Ф M (Au)=5.1eV. For semiconductors, the work function is: which is shown in figure 2. According to known conditions, the electron affinity of Si is and the Bandgap energy of silicon is The Fermi potential Ф F is equal to and is about 25mV at 300k. Thus, Fermi potential: and the work function of semiconductors: The definition of Mental-Semiconductors work function difference is: Thus, the work function difference: Figure 2: Energy band diagram explaining work function

These formulas have been used: and C MAX has been calculated in task 2, which is 2.92Nf. assuming that it is a uniformly doped semiconductor, then and, so that,   It is not a simple function and cannot be calculate directly, in this case, we use MATLAB to calculate the N A , and N A =4.2*10 21 m -3

 The equivalent oxide thickness is stated as a distance, which imply the thickness of silicon oxide that is required to get the similar effect as using high-k materials. The term is commonly used to describe the field effect transistors and is often given in nanometers. These formulas have been used: so that, and we can figure out that ε hk=10.6506 while ， we can get that EOT=2.8084nm.

  The oxide relative permittivity can be calculated using the mathematical characteristics of capacitors under the accumulation region (which is the highest region of the C-V plot). Under the accumulation condition, the MOS capacitor can be seen as the series connection of the C ox and C acc .            As C acc is exponentially dependent on and therefore very large.  (C acc =dC acc /d Φ S )  So, in above equation, the term of accumulation capacitance can be ignored and the total capacitance can be seen equal to oxide capacitance. Then we can obtain the oxide capacitance by reading the max value from the C-V plot, from given data, the value is 2.92E+03pF. Then we can calculate the oxide relative permittivity through function below: With given data, we have: By substituting equations 2.2 to 2.5 into equation 2.1, we obtained  ε ox =6.8.

  The data was allocated in txt format and we put them into excel and obtained this C-V plot. Figure 1: C-V plot C-V plot (HfSiO, 70% Hf). According to the plot drawn from given data, the substrate involved in this project is p type. This conclusion is made from the characteristic of surface field effect. There are three conditions of the energy band diagram, accumulation, depletion and inversion. Under the accumulation condition of p type Si MOS system, when negative voltage is applied on the gate, positive holes in the semiconductor will be attracted to the region close to the oxide and accumulate there. When voltage applied on the gate increases to positive, the positive holes accumulated before will be repelled and leave behind some negative acceptances. Then this condition is called depletion condition. Finally, when the gate voltage is high enough, the fermi level of semiconductor in the region near to the oxide will be bend higher than the intrinsic level, and thus...

  The object of this project is thin high-k gate stacks (HfSiO, 70%), which is bind up with MOSFET, while silicon-based integrated circuits have developed rapidly in the past years. High-k dielectric materials are one of the most popular research topics in the micro electronic industry. By using some special properties of some high-k dielectric materials, some new devices may be conducted and the limitation of the thin gate-oxide faced in semiconductor industry may be solved. Electronics based on these improve the life quality and make our life more comfortable, like internet and mobile phones. On the basis of Moore’s law, the number of transistors on the integrated circuits doubled every two years, so that the gate stacks become the concern issue. Scientists and engineers made great efforts to incorporate the high-k dielectric into a transistor. According to SIA [1], in order to maintain the development speed of the semiconductor, researchers should develop constraints like new ...